Abstract
- 5 stages - Fetch, Decode, Read, Execute & Write Back
- When one stage is running, the other stages will be idle. This can be optimised with Instruction-Level Parallelism
Fetch
- Retrieve Instruction from RAM
- Handled by Program Counter & Instruction Register
Decode
- Handled by Control Unit
Execute
- Where the execution of Instruction is performed, can be further beak down to Read & Write Back
Read
- Retrieve required data from Main Memory or Register
Write Back
- Result is stored back into Main Memory or Register